This invention relates generally to output buffer circuits with reduced noise characteristics. More particularly, the present invention relates to output buffer circuits which have a significant reduction in power or ground bounce noise when multiple outputs are being simultaneously switched.
As is generally well-known in the art, output buffer circuits or drivers are commonly used in digital logic circuits in order to cause an output signal to make rapid transitions between a low voltage representing a "0" logic state and a higher voltage representing a "1" logic state and vice-versa. Typically, the output buffer circuit implemented in complementary metal-oxide-semiconductor (CMOS) process technology includes a P-channel pull-up transistor device and an N-channel pull-down transistor device connected in series between respective first and second power supply terminals. The drains of the pull-up and pull-down transistor devices are connected together, which is connected to an output node to provide the output signal. The gates of the pull-up and pull-down transistor devices are connected to internal nodes adapted to receive respective control signals.
The pull-up and pull-down transistor devices are usually quite large in size since they must usually output a large drive current which may be necessary to meet the input requirements of another circuit that uses the output signal from the output buffer circuit. It is always desirable to have faster switching speeds and noise suppression in high-speed digital circuits, especially when the digital circuits are formed on the same substrate of a semiconductor integrated circuit chip with a high density of components. However, as the switching speed is increased by increasing the current drive capability of the output buffer circuit, parasitic inductances associated with the interconnection of the output node to an output terminal pin and with the connection of the transistor sources to power supply terminal pins will cause greater noise to be generated. This increased noise can interfere with the functioning of the circuit components which interface with the output buffer circuit. Thus, the trends toward higher packing density of components on a semiconductor integrated circuit chip make noise reduction or suppression especially important in output buffer circuit designs.
One form of unwanted noise generated by an output buffer circuit is referred to as "ground bounce" which is a voltage ground fluctuation induced by the switching of its output node from the higher voltage level to the low voltage level. During this high-to-low transition, a transient ground current is generated which causes oscillations or inductive ringing to appear at the output node. In particular, the magnitude of the ground bounce is larger when the voltage switching range increases or when the output current of the buffer circuit is larger. Since a ground line is shared by many devices on the integrated circuit chip, the ground bounce, if it is sufficiently large, may degrade the output voltage level (logic "1" or logic "0") causing interface problems among the output buffer circuit and other integrated circuits. A similar phenomenon referred to as "power or supply bounce" occurs when the output node is making a low-to-high transition.
Further, as the technology for manufacturing such semiconductor integrated circuit devices has advanced the number of parallel bits of information processed by such devices has increased as well. For example, in the microcomputer field a typical integrated circuit memory device may have multiple outputs consisting of 8, 16, 32 or even 64 parallel bits. As a result, with the increased number of parallel bits being outputted by such devices the number of output buffer circuits is correspondingly increased, thereby increasing the total noise generated during transitions. It should be noted that the ground or power bounce problem is even further magnified when a plurality of output buffer circuits have their outputs being simultaneously switched. In other words, for instance when eight output nodes are being switched from high-to-low at the same time, the total voltage change on the common ground line may be equal to 8 times the voltage fluctuation as when only one output node is being switched.
Various approaches have been made heretofore in the prior art of output buffer design so as to solve the problem of undesired power/ground bounce noise without sacrificing the needed high-speed of operation. One technique of the prior art for controlling output noise is depicted in FIG. 1, which illustrates a simplified schematic circuit diagram of a conventional output buffer circuit 10a formed as a portion of a semiconductor integrated circuit chip 11. The output buffer circuit 10a is comprised of an output driver stage 12, a first pre-driver stage 14, and a second pre-driver stage 16. The output driver stage 12 is formed of a P-channel MOS pull-up drive transistor 18 and an N-channel MOS pull-down drive transistor 20 coupled in series between respective first and second power supply pads 22, 24.
The first power supply pad 22 may be supplied with a positive voltage or potential VDD which is coupled to an internal power supply node VL1 via a lead line having parasitic inductance L1. The source of the drive transistor 18 is also connected to the node VL1. The parasitic inductance L1 represents a package inductance associated with the pad 22 itself and the wiring used to connect the source of the drive transistor 18 to the pad 22. The second power supply pad 24 may be supplied with a ground potential VSS which is coupled to an internal ground potential node VL2 via a lead line having parasitic inductance L2. Similarly, the parasitic inductance L2 represents a package inductance associated with the pad 24 itself and the wiring used to connect the source of the drive transistor 20 to the pad 24.
The drains of the drive transistors 18 and 20 are connected together and further joined to an internal node 26. The internal node 26 is also connected to an output pad 28 via a lead connection having parasitic inductance L3. The parasitic inductance L3 represents a package inductance associated with the output pad 28 itself and the wiring used to connect the drains of the transistors 18, 20 to the pad 28. An output signal OUT.sub.i is provided at the output pad 28 of the buffer circuit 10a and is used to drive a capacitive load CL connected between the pad 28 and the ground potential VSS. It should be understood that the output buffer circuit 10a is but for one bit only and that typical semiconductor integrated circuit devices such as memory devices having multiple outputs (e.g., 8 bits) would require a corresponding number of buffer circuits.
Further, the first pre-driver stage 14 includes an inverter 30 having its input connected to receive an input drive signal DSO.sub.i and its output connected to the gate of the drive transistor 18. The second pre-driver stage 16 includes an inverter 32 having its input connected also to receive the input drive signal DSO.sub.i and its output connected to the gate of the drive transistor 20. As is conventional, each of the CMOS inverters 30, 32 is formed of a P-channel MOS transistor and an N-channel MOS transistor whose gates are connected together to form its input and whose drains are connected together to form its output. The sources of the P-channel transistors are coupled to the positive voltage VDD, and the sources of the N-channel transistors are coupled to the ground potential VSS.
In order to control the drive current applied to the gate of the drive transistor 20 during a high-to-low transition, a source pull-down resistor R.sub.Di is connected between the positive voltage VDD and the source of the P-channel transistor in the inverter 32. When the output signal OUT.sub.i is switched from high to low in response to the drive signal DSO.sub.i causing the drive transistor 20 to turn on, a current I is quickly discharging from the capacitive load CL through the parasitic inductance L3, drive transistor 20, and parasitic inductance L2 to the ground potential VSS. The instantaneous voltage induced on the source (node VL2) of the drive transistor 20 will be equal to L2.times.dI/dt causing the ground bounce noise. The source resistor R.sub.Di will reduce the drive current to the gate of the drive transistor 20 and thus slows down its turn-on time, thereby reducing the drive current and the ground bounce noise. Similarly, a source pull-up resistor R.sub.Ui is connected between the ground potential VSS and the source of the N-channel transistor in the inverter 30 so as to control the drive current applied to the gate of the drive transistor 18 during a low-to-high transition.
However, this approach suffers from the disadvantage of requiring the use of an increased number of circuit components (e.g., a large number of resistors R.sub.Ui, R.sub.Di) which occupies a large amount of chip area. A second technique of the prior art to solve the power/ground bounce problem is shown in FIG. 2. The second technique is quite similar to the first one and utilizes an output buffer circuit 10b having constant current sources. As can be seen, the source resistor R.sub.Ui is replaced by a first constant current source I.sub.Ui and the source resistor R.sub.Di is replaced by a second constant current source I.sub.Di. Nevertheless, it should be apparent that this second technique still suffers from all of the same drawbacks as the first technique.
The output buffer circuits of the present invention represents a significant improvement over the abovedescribed prior art buffer circuits so as to reduce power/ground bounce noise when multiple outputs thereof are being simultaneously switched. This is achieved by the provision of a shared pull-up resistor connected between a first pre-driver stage inverter and the ground potential and a shared pull-down resistor connected between a second pre-driver stage inverter and the power supply potential.